Add SystemVerilog support

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Sean McLoughlin authored and David Peter committed 2021-03-15 07:21:15 +01:00

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commit d89fa3ebc2

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assets/syntaxes/02_Extra/SystemVerilog

Vendored Submodule

+1

Submodule assets/syntaxes/02_Extra/SystemVerilog added at 7eca705e87.