Add SystemVerilog support

src/assets.rs

@@ -450,6 +450,7 @@ mod tests {
         assert_eq!(test.syntax_for_file("test.sass"), "Sass");
         assert_eq!(test.syntax_for_file("test.js"), "JavaScript (Babel)");
         assert_eq!(test.syntax_for_file("test.fs"), "F#");
+        assert_eq!(test.syntax_for_file("test.v"), "Verilog");
     }
 
     #[test]